`timescale 1ns/1ps

module tb_IIR_top;

    parameter in_clk = 500_000_000;  // 500 MHz
    parameter datin_width = 16;
    parameter daout_width = 16;
    parameter mux_num = 10;

    reg clk;
    reg rst_n;
    reg start;
    reg [datin_width*mux_num-1:0] data_in;
    wire finished;
    wire [daout_width*mux_num-1:0] data_out;

    // Instantiate the design under test (DUT)
    IIR_top #(
        .in_clk(in_clk),
        .datin_width(datin_width),
        .daout_width(daout_width),
        .mux_num(mux_num)
    ) dut (
        .clk(clk),
        .rst_n(rst_n),
        .start(start),
        .data_in(data_in),
        .finished(finished),
        .data_out(data_out)
    );

    // Clock generation: 2ns period => 500MHz
    initial clk = 0;
    always #1 clk = ~clk;

    // Task to apply start signal
    task start_once;
        begin
            start <= 1;
            @(posedge clk);
            start <= 0;
        end
    endtask

    integer i;
    integer cycle_counter = 0;

    initial begin
        // Init
        rst_n = 0;
        start = 0;
        data_in = 0;

        // Reset
        repeat(5) @(posedge clk);
        rst_n = 1;

        // Initialize data input with 0~9 (each 16-bit)
        for (i = 0; i < mux_num; i = i + 1) begin
            data_in[i*datin_width +: datin_width] = i;
        end

        // Simulation main loop
        cycle_counter = 0;

        repeat (6000) begin
            @(posedge clk);
            cycle_counter = cycle_counter + 1;

            // 每500拍拉高start，持续1拍
            if (cycle_counter % 500 == 0) begin
                start_once();
            end
        end

        $display("Simulation done.");
        $stop;
    end

endmodule
